Semiconductor memory device

A memory has a first bit line pair, a second bit line pair, a third bit line pair, a first data line pair, a second data line pair, a first transistor pair connecting the first bit line pair to the first data line pair, a second transistor pair connecting the second bit line pair to the second data...

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Hauptverfasser: MAGOME, KOICHI
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creator MAGOME
KOICHI
description A memory has a first bit line pair, a second bit line pair, a third bit line pair, a first data line pair, a second data line pair, a first transistor pair connecting the first bit line pair to the first data line pair, a second transistor pair connecting the second bit line pair to the second data line pair, a third transistor pair connecting the third bit line pair to the first data line pair, a fourth transistor pair connecting the third bit line pair to the second data line pair, a first selection line connected to the first transistor pair for switching ON/OFF of the first transistor pair, a second selection line connected to the second transistor pair for switching ON/OFF of the second transistor pair, a third selection line connected to the third transistor pair for switching ON/OFF of the third transistor pair, and a fourth selection line connected to the fourth transistor pair for switching ON/OFF of the fourth transistor pair.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5566128A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5566128A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5566128A3</originalsourceid><addsrcrecordid>eNrjZJAOTs3NTM7PSylNLskvUshNzc0vqlRISS3LTE7lYWBNS8wpTuWF0twM8m6uIc4euqkF-fGpxQWJyal5qSXxocGmpmZmhkYWjsaEVQAAEp0jFg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor memory device</title><source>esp@cenet</source><creator>MAGOME; KOICHI</creator><creatorcontrib>MAGOME; KOICHI</creatorcontrib><description>A memory has a first bit line pair, a second bit line pair, a third bit line pair, a first data line pair, a second data line pair, a first transistor pair connecting the first bit line pair to the first data line pair, a second transistor pair connecting the second bit line pair to the second data line pair, a third transistor pair connecting the third bit line pair to the first data line pair, a fourth transistor pair connecting the third bit line pair to the second data line pair, a first selection line connected to the first transistor pair for switching ON/OFF of the first transistor pair, a second selection line connected to the second transistor pair for switching ON/OFF of the second transistor pair, a third selection line connected to the third transistor pair for switching ON/OFF of the third transistor pair, and a fourth selection line connected to the fourth transistor pair for switching ON/OFF of the fourth transistor pair.</description><edition>6</edition><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>1996</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19961015&amp;DB=EPODOC&amp;CC=US&amp;NR=5566128A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25566,76549</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19961015&amp;DB=EPODOC&amp;CC=US&amp;NR=5566128A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MAGOME; KOICHI</creatorcontrib><title>Semiconductor memory device</title><description>A memory has a first bit line pair, a second bit line pair, a third bit line pair, a first data line pair, a second data line pair, a first transistor pair connecting the first bit line pair to the first data line pair, a second transistor pair connecting the second bit line pair to the second data line pair, a third transistor pair connecting the third bit line pair to the first data line pair, a fourth transistor pair connecting the third bit line pair to the second data line pair, a first selection line connected to the first transistor pair for switching ON/OFF of the first transistor pair, a second selection line connected to the second transistor pair for switching ON/OFF of the second transistor pair, a third selection line connected to the third transistor pair for switching ON/OFF of the third transistor pair, and a fourth selection line connected to the fourth transistor pair for switching ON/OFF of the fourth transistor pair.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1996</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAOTs3NTM7PSylNLskvUshNzc0vqlRISS3LTE7lYWBNS8wpTuWF0twM8m6uIc4euqkF-fGpxQWJyal5qSXxocGmpmZmhkYWjsaEVQAAEp0jFg</recordid><startdate>19961015</startdate><enddate>19961015</enddate><creator>MAGOME; KOICHI</creator><scope>EVB</scope></search><sort><creationdate>19961015</creationdate><title>Semiconductor memory device</title><author>MAGOME; KOICHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5566128A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1996</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>MAGOME; KOICHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MAGOME; KOICHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor memory device</title><date>1996-10-15</date><risdate>1996</risdate><abstract>A memory has a first bit line pair, a second bit line pair, a third bit line pair, a first data line pair, a second data line pair, a first transistor pair connecting the first bit line pair to the first data line pair, a second transistor pair connecting the second bit line pair to the second data line pair, a third transistor pair connecting the third bit line pair to the first data line pair, a fourth transistor pair connecting the third bit line pair to the second data line pair, a first selection line connected to the first transistor pair for switching ON/OFF of the first transistor pair, a second selection line connected to the second transistor pair for switching ON/OFF of the second transistor pair, a third selection line connected to the third transistor pair for switching ON/OFF of the third transistor pair, and a fourth selection line connected to the fourth transistor pair for switching ON/OFF of the fourth transistor pair.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record>
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subjects INFORMATION STORAGE
PHYSICS
STATIC STORES
title Semiconductor memory device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-18T10%3A04%3A40IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MAGOME;%20KOICHI&rft.date=1996-10-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS5566128A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true