Semiconductor memory device

A memory has a first bit line pair, a second bit line pair, a third bit line pair, a first data line pair, a second data line pair, a first transistor pair connecting the first bit line pair to the first data line pair, a second transistor pair connecting the second bit line pair to the second data line pair, a third transistor pair connecting the third bit line pair to the first data line pair, a fourth transistor pair connecting the third bit line pair to the second data line pair, a first selection line connected to the first transistor pair for switching ON/OFF of the first transistor pair, a second selection line connected to the second transistor pair for switching ON/OFF of the second transistor pair, a third selection line connected to the third transistor pair for switching ON/OFF of the third transistor pair, and a fourth selection line connected to the fourth transistor pair for switching ON/OFF of the fourth transistor pair.