PROM IC enabling a stricter memory cell margin test

A sense circuit includes a sense amplifier and a pull-up resistor circuit disposed on the input side of the sense amplifier. In response to a test selection signal, a read voltage applying circuit applies an external voltage to a selected memory cell and the total resistance of the resistor circuit...

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Bibliographische Detailangaben
Hauptverfasser: UENOYAMA, HIROMI, TADA, YOSHIHIRO
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A sense circuit includes a sense amplifier and a pull-up resistor circuit disposed on the input side of the sense amplifier. In response to a test selection signal, a read voltage applying circuit applies an external voltage to a selected memory cell and the total resistance of the resistor circuit is switched from a normal resistance to a smaller resistance for testing. Since the input side of the sense amplifier is pulled up through the resistor circuit with the resistance for testing, it is possible to detect the storage state of the selected memory cell under a stricter condition.