Interlocked restore circuit
A low power, high speed, multistage asynchronous logic circuit having an interlocked restore mechanism. A first logic circuit detects a valid input signal and drives an output to a second logic circuit. The second logic circuit receives inputs from the first logic circuit and drives a data ready sig...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A low power, high speed, multistage asynchronous logic circuit having an interlocked restore mechanism. A first logic circuit detects a valid input signal and drives an output to a second logic circuit. The second logic circuit receives inputs from the first logic circuit and drives a data ready signal back to the first logic circuit when it detects the output from the first logic circuit. The first logic circuit resets when it receives the data ready signal from the second logic circuit and it detects that its inputs have been reset. |
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