Expandable high performance FIFO design which includes memory cells having respective cell multiplexors
An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided w...
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creator | AMINI NADER BRANNON SHERWOOD LOHMAN TERENCE J BOURY BECHARA E |
description | An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry. |
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The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry.</description><edition>6</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>1996</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19960827&DB=EPODOC&CC=US&NR=5551009A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19960827&DB=EPODOC&CC=US&NR=5551009A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AMINI; NADER</creatorcontrib><creatorcontrib>BRANNON; SHERWOOD</creatorcontrib><creatorcontrib>LOHMAN; TERENCE J</creatorcontrib><creatorcontrib>BOURY; BECHARA E</creatorcontrib><title>Expandable high performance FIFO design which includes memory cells having respective cell multiplexors</title><description>An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1996</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqFiz0KwkAUBtNYiHoG3wWEiKSwlJCglYVah3XzZffB_rGbxHh7g9hbDQwzy0xVUxCuFU8D0qw0BcTORyucBNWX-kotEitHL81SEztphtmQhfXxTRLGJNJiZKcoIgXInkd8PdnB9BwMJh_TOlt0wiRsflxl27q6l-cdgm_mT0g49M3jVhTFPs-Pp8P_4gPFNj-T</recordid><startdate>19960827</startdate><enddate>19960827</enddate><creator>AMINI; NADER</creator><creator>BRANNON; SHERWOOD</creator><creator>LOHMAN; TERENCE J</creator><creator>BOURY; BECHARA E</creator><scope>EVB</scope></search><sort><creationdate>19960827</creationdate><title>Expandable high performance FIFO design which includes memory cells having respective cell multiplexors</title><author>AMINI; NADER ; BRANNON; SHERWOOD ; LOHMAN; TERENCE J ; BOURY; BECHARA E</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5551009A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1996</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>AMINI; NADER</creatorcontrib><creatorcontrib>BRANNON; SHERWOOD</creatorcontrib><creatorcontrib>LOHMAN; TERENCE J</creatorcontrib><creatorcontrib>BOURY; BECHARA E</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AMINI; NADER</au><au>BRANNON; SHERWOOD</au><au>LOHMAN; TERENCE J</au><au>BOURY; BECHARA E</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Expandable high performance FIFO design which includes memory cells having respective cell multiplexors</title><date>1996-08-27</date><risdate>1996</risdate><abstract>An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. 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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
title | Expandable high performance FIFO design which includes memory cells having respective cell multiplexors |
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