Expandable high performance FIFO design which includes memory cells having respective cell multiplexors

Expandable high performance FIFO design which includes memory cells having respective cell multiplexors

An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided w...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: AMINI, NADER, BRANNON, SHERWOOD, LOHMAN, TERENCE J, BOURY, BECHARA E
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry.