Parallel programming of field programmable gate array devices

Method and apparatus for rapidly configuring several field programmable gate arrays ("CFPGAs"), some of which FPGAs are of different sizes. In accordance with the present invention, the configuration is provided to each FPGA in parallel, on a bit-wise basis. Further, the different sizes of FPGA are accommodated by utilizing dummy bits in the configuration data. Still further, the configuration process can be completed at different times, i.e., the completion times of the configuration process can be staggered, by use of dummy bits in the configuration data.