Multiprocessor interrupt controller with remote reading of interrupt control registers

A multiprocessor programmable interrupt controller (MPIC) system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt-related messages. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus for broadcasting of I/O-generated interrupt request messages. Each processor chip has an on-board interrupt acceptance unit (IAU) that can accept interrupt requests from the interrupt bus and can broadcast on the interrupt bus interrupt request messages generated by its associated processor. Each processor can request to read the contents of the IAU control registers that are associated with another target processor. In that case, a remote read request message is generated by the IAU of the local processor and responded to, without software intervention, by the IAU of the target processor. A remote read status field indicates to the local processor the status of the data contained in a remote read register. The remote IAU is expected to respond in a fixed number of interrupt bus cycles. If the remote agent is unable to do so, then the remote read status field becomes "Invalid." If successful, the remote read status resolves to "Valid." The processor polls this field to determine the completion and success of the remote read request. Remote read requests are always successful (although the data may be valid or invalid) in that they are never retried. Remote read requests are primarily a debug feature, and a "hung" remote IAU that is unable to respond to a remote read request should not cause the debugging software to hang on the local processor.