Analog to digital convertor

There are provided n signal processing units for sampling an analog signal based on n [references] reference voltages, k intermediate signal processing units for comparing two intermediate signals outputted from two adjacent signal processing units in n signal processing units, and an encoder for coding logical output values of the signal processing unit and the intermediate signal processing unit. One signal processing unit includes a differential amplifier, a comparison circuit and logic circuit, and one intermediate signal processing unit includes another comparison circuit and another logic circuit. As a result, when an analog signal is applied to the signal processing unit, a reciprocal of a potential difference between a reference voltage and an analog signal is increased by a gain [times] G, and [the] an intermediate signal is outputted to the comparison circuit of the intermediate signal processing unit. Further, comparison signals of the comparison circuit of the signal processing unit and the comparison circuit of the intermediate signal processing unit are quantized by the logic circuit of the signal processing unit, and comparison signals of the comparison circuit of the intermediate signal processing unit and the comparison circuit of the signal processing unit are quantized by the logic circuit of the intermediate signal processing unit. With this, n+k logical output signals quantized by the logic circuits of n signal processing units and the logic circuits of k intermediate signal processing units are coded by the encoder, thus obtaining a digital output signal in N bits.