Voltage multiplier using switched capacitance technique

A voltage multiplier is constructed using a series combination of capacitors and an associated switching circuit which provides for charging each capacitor in the series by sequentially connecting each capacitor to a d.c. input voltage. The number of capacitors in the series combination is selectabl...

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Bibliographische Detailangaben
Hauptverfasser: JANSEN, MARINUS J
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A voltage multiplier is constructed using a series combination of capacitors and an associated switching circuit which provides for charging each capacitor in the series by sequentially connecting each capacitor to a d.c. input voltage. The number of capacitors in the series combination is selectable by the user. The d.c. input voltage of N volts is converted to an a.c. output voltage of peak-to-peak N+1 times the input voltage developed off a tap in the series combination using the pattern of sequential switching. The choice of tap determines the relative offset voltage of the output waveform desired. The relative charging times of the capacitors are chosen so that the output waveform resembles a sine wave to minimize the production of harmonics.