Merged decoding circuit for analog-to-digital flash conversion

A circuit for conversion of an analog input signal to a digital representation of the analog signal. The circuit is typically employed in flash technology, since it is able to produce the digital representation of the analog signal faster and more efficiently than conventional flash converters. The circuit includes a plurality of resistors serially coupled between two reference voltages to form a plurality of nodes therebetween. A plurality of comparators, each having a first input coupled to one of the plurality of nodes and a second input coupled to the analog input signal. Accordingly each comparator compares the analog input signal to a voltage potential at one of the nodes to generate first and second complementary output signals at the outputs of the comparators. The complementary outputs are then applied to a decode circuit having a plurality of digital output lines and switches directly coupled to the digital output lines. The decode circuit exploits a numerical characteristic of digital numbering systems to reduce the amount of hardware required, and as a result achieves improved performance. The first and second complementary outputs switch the digital output lines to a first or second logic state in response to the first and second complementary output signals, thereby producing the digital representation of the analog input signal.