Digital integrating circuit device

To provide a digital integrating circuit which can increase speed by preventing the influence of a delay in carry propagation and can obtain an accumulated value for each section at a higher sampling frequency, the carry holding type adder 4 and the carry propagation type adder 7 are combined and a plurality of holding registers 51 to 53 and a plurality of result storage registers 81 to 83 are provided to store the results of additions. A single holding register is effective for each section and these holding registers 51 to 53 are structured as shift registers after completion of accumulation for all the sections so that accumulated data stored in the holding registers are sequentially input into the carry propagation type adder to output final accumulated data for each section.