Multistate microprocessor bus arbitration signals

A microprocessor bus arbitration communications scheme for enhancing efficiency and performance of a multi-master bus system, typically within a computer system, including a central processing unit ("CPU") being a primary bus master, a bus arbiter and at least one alternative bus master coupled together by a bus. The CPU includes an internal memory element, a bus queue and bus control logic which collectively operate to generate a plurality of microprocessor bus arbitration signals to the bus arbiter. These microprocessor bus arbitration signals include a first bus arbitration signal indicating whether the CPU requires access to the bus and a second bus arbitration signal indicating that the CPU requires immediate access to the bus.