Dynamic memory device having a plurality of internal power sources

Disclosed therein is a dynamic memory device having an internal power source circuit generating an internal power voltage which is smaller than an external power voltage applied to the device and supplied to an internal memory circuit as an operating voltage. The internal power source circuit includes a differential amplifier for stabilizing the internal power voltage in response to a reference voltage, and a current flowing through the differential amplifier is controlled to a first value during a standby mode, a second value larger than the first value during a data sensing operation and restoring (refreshing) operation of an active mode, and a third value larger than the first value but smaller than the second value during the other operation of the active mode.