Dynamic validity facility for fast purging of translation bypass buffers
An address translation mechanism that allows for the creation, use, and purging of Translation Lookaside Buffer (TLB) entries associated to a unique task (virtual machine or guest). This association between guest and TLB entry allows for reuse of guest TLB entries (sets) in a multitasking system, qu...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | An address translation mechanism that allows for the creation, use, and purging of Translation Lookaside Buffer (TLB) entries associated to a unique task (virtual machine or guest). This association between guest and TLB entry allows for reuse of guest TLB entries (sets) in a multitasking system, quick purging of TLB entries during transition between address translation states, and quick restoration of control program TLB entries. The address translation mechanism as described herein must contain, at a minimum, a translation lookaside buffer; each entry must contain, at least: a absolute address field, a virtual address field and a translation mode indicator (TMI); a guest TMI table having entries containing a unique identifier to a guest and an associated TMI value; and a TMI register that holds the currently valid TMI. |
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