Memory efficient gate array cell

A core cell (10) for a gate array circuit has been provided. The core cell has a transistor layout that facilitates efficient memory circuit design within the gate array. The core cell includes a first (14-22) and second (23-31) plurality of transistors of a first conductivity type, and a third plurality (52-63) of transistors of a second conductivity type wherein the third plurality of transistors are positioned between the first and second plurality of transistors. The third plurality of transistors having transistors of a first and second size wherein at least two transistors of the second size of the third plurality of transistors includes a common gate connection.