Method of computing multi-conductor parasitic capacitances for VLSI circuits

A method of computing parasitic capacitances between multiple electrical conductors within an electric circuit computes a division of the circuit's physical layout into a plurality of windows. The parasitic capacitances associated with the conductors of each window are computed, and the results for the various windows combined into a matrix of parasitic capacitances for the overall circuit. The windows are preferably overlapped, with the capacitance values for conductor pairs located in more than one window averaged. Complex polygons are fractured into simpler shapes by extending a ray from a vertex of the polygon to intersect an opposed segment, and defining the peripheries of the simpler elements as comprising the ray and respective different portions of the original polygon's periphery. Rays may be extended in a x,y pattern from multiple vertices of the polygon until a ray is located that extends through the polygon's interior, with the fracturing performed along that ray. Fracturing preferably continues until all of the elements are reduced to Manhattan-oriented rectangles or triangles. Where one element overlaps another element in another plane, fracturing is performed along a projection of the overlapping edge on the second element to reduce inaccuracies in the approximated charge density on the overlapped element.