Configuration apparatus for determining relative position of a cache memory in a cache memory array

A cache memory which includes a cache controller formed on a single substrate. A plurality of the memories may be used in an array. The memories themselves determine how many other memories are in an array and each of their relative positions in the array. From this information, each memory sets the range of its set fields and the size of its tag fields. This is done on reset with the configuration information being distributed among the memories themselves, without being centrally stored, and in a manner transparent to the software.