Flexible graphics interface device switch selectable big and little endian modes, systems and methods
A circuit 83, 97 is provided for selectively interpreting data received in a format selected from the big-endian and little-endian formats to an other one of the big-endian and little-endian formats and includes an array of j sequentially ordered data input terminals for receiving a j-bit word of da...
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Zusammenfassung: | A circuit 83, 97 is provided for selectively interpreting data received in a format selected from the big-endian and little-endian formats to an other one of the big-endian and little-endian formats and includes an array of j sequentially ordered data input terminals for receiving a j-bit word of data formatted in a preselected one of the big-endian and little-endian formats. An array of j sequentially ordered first AND gates 126 is provided, each first AND gate 126 having first and second input ports and an output port, the first input port of the nth first AND gate 126 coupled to the nth one of the input terminals, the second input ports of the first AND gates 126 coupled to a control signal. An array of j sequentially ordered second AND gates 128 are provided, and each second AND gate 128 having first and second input ports and an output port, of the first input port of an nth one of the second AND gates 128 coupled to a (j-n+1)th one of the first input terminals, the second input ports of the second AND gates 128 are coupled to a second control. An array of j sequentially ordered OR gates 130 are provided each having first and second input ports and an output port, the first input port of an mth one of the OR gates 130 being coupled to the output of an mth one of the first AND gate 126, the second input port of an nth one of the OR gates 130 coupled to the output of the nth one of the second AND gates 128. Wherein j is a consonant, n is a variable between 1 and j, and m is a variable between 1 and j. |
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