Room-temperature tunneling hot-electron transistor

A hot-electron transistor (10) is formed on substrate (12) having an outer surface. The present transistor includes subcollector layer (14) comprising Indium Gallium Arsenide formed outwardly from the outer surface of substrate (12). Collector barrier layer (18) comprising Indium Aluminum Gallium Arsenide is outwardly formed from subcollector layer (14), and collector barrier layer (18) minimizes leakage current in transistor (10). Outwardly from collector barrier layer (18) is formed base layer (20) comprising Indium Gallium Arsenide. Tunnel injector layer (21) comprising Aluminum Arsenide for ballistically transporting electrons in transistor (10) is outwardly formed from base layer (20), and emitter layer (24) comprising Indium Aluminum Arsenide is outwardly formed from tunnel injector layer (21).