Odd-number frequency divider and method of constituting the same
A first odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2n+1] frequency-divided signal, a register havin...
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creator | ABE MASATO SEKI FUSAO |
description | A first odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2n+1] frequency-divided signal, a register having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for shifting the 1/[2n+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the [n-1]th flip-flop circuit of the register synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the nth flip-flop circuit and outputting the 1/[2n+1] frequency-divided signal. A second odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected m [m=3 to m] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2m+1] frequency-divided signal, a register having cascade-connected [m+1] elements of flip-flop circuits for shifting the 1/[ 2m+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the mth flip-flop circuit synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the [m+1]th flip-flop circuit and outputting the 1/[2m+1] frequency-divided signal. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5438600A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5438600A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5438600A3</originalsourceid><addsrcrecordid>eNrjZHDwT0nRzSvNTUotUkgrSi0sTc1LrlRIySzLTAGKJOalKOSmlmTkpyjkpykk5-cVl2SWlJZk5qUrlGSkKhQn5qbyMLCmJeYUp_JCaW4GeTfXEGcP3dSC_PjU4oLE5NS81JL40GBTE2MLMwMDR2PCKgAP7jCm</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Odd-number frequency divider and method of constituting the same</title><source>esp@cenet</source><creator>ABE; MASATO ; SEKI; FUSAO</creator><creatorcontrib>ABE; MASATO ; SEKI; FUSAO</creatorcontrib><description>A first odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2n+1] frequency-divided signal, a register having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for shifting the 1/[2n+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the [n-1]th flip-flop circuit of the register synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the nth flip-flop circuit and outputting the 1/[2n+1] frequency-divided signal. A second odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected m [m=3 to m] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2m+1] frequency-divided signal, a register having cascade-connected [m+1] elements of flip-flop circuits for shifting the 1/[ 2m+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the mth flip-flop circuit synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the [m+1]th flip-flop circuit and outputting the 1/[2m+1] frequency-divided signal.</description><edition>6</edition><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; STATIC STORES</subject><creationdate>1995</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950801&DB=EPODOC&CC=US&NR=5438600A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19950801&DB=EPODOC&CC=US&NR=5438600A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ABE; MASATO</creatorcontrib><creatorcontrib>SEKI; FUSAO</creatorcontrib><title>Odd-number frequency divider and method of constituting the same</title><description>A first odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2n+1] frequency-divided signal, a register having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for shifting the 1/[2n+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the [n-1]th flip-flop circuit of the register synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the nth flip-flop circuit and outputting the 1/[2n+1] frequency-divided signal. A second odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected m [m=3 to m] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2m+1] frequency-divided signal, a register having cascade-connected [m+1] elements of flip-flop circuits for shifting the 1/[ 2m+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the mth flip-flop circuit synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the [m+1]th flip-flop circuit and outputting the 1/[2m+1] frequency-divided signal.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1995</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHDwT0nRzSvNTUotUkgrSi0sTc1LrlRIySzLTAGKJOalKOSmlmTkpyjkpykk5-cVl2SWlJZk5qUrlGSkKhQn5qbyMLCmJeYUp_JCaW4GeTfXEGcP3dSC_PjU4oLE5NS81JL40GBTE2MLMwMDR2PCKgAP7jCm</recordid><startdate>19950801</startdate><enddate>19950801</enddate><creator>ABE; MASATO</creator><creator>SEKI; FUSAO</creator><scope>EVB</scope></search><sort><creationdate>19950801</creationdate><title>Odd-number frequency divider and method of constituting the same</title><author>ABE; MASATO ; SEKI; FUSAO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5438600A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1995</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>ABE; MASATO</creatorcontrib><creatorcontrib>SEKI; FUSAO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ABE; MASATO</au><au>SEKI; FUSAO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Odd-number frequency divider and method of constituting the same</title><date>1995-08-01</date><risdate>1995</risdate><abstract>A first odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2n+1] frequency-divided signal, a register having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for shifting the 1/[2n+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the [n-1]th flip-flop circuit of the register synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the nth flip-flop circuit and outputting the 1/[2n+1] frequency-divided signal. A second odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected m [m=3 to m] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2m+1] frequency-divided signal, a register having cascade-connected [m+1] elements of flip-flop circuits for shifting the 1/[ 2m+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the mth flip-flop circuit synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the [m+1]th flip-flop circuit and outputting the 1/[2m+1] frequency-divided signal.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES |
title | Odd-number frequency divider and method of constituting the same |
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