Odd-number frequency divider and method of constituting the same

A first odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2n+1] frequency-divided signal, a register havin...

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Hauptverfasser: ABE, MASATO, SEKI, FUSAO
Format: Patent
Sprache:eng
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Zusammenfassung:A first odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2n+1] frequency-divided signal, a register having cascade-connected n [n=1, 2, 3] elements of flip-flop circuits for shifting the 1/[2n+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the [n-1]th flip-flop circuit of the register synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the nth flip-flop circuit and outputting the 1/[2n+1] frequency-divided signal. A second odd-number frequency divider for frequency-dividing and outputting an input signal of optional frequency includes a counter having cascade-connected m [m=3 to m] elements of flip-flop circuits for receiving an input signal and outputting a 1/[2m+1] frequency-divided signal, a register having cascade-connected [m+1] elements of flip-flop circuits for shifting the 1/[ 2m+1] frequency-divided signal successively synchronously with the input signal, a latch circuit for holding a register output signal of the mth flip-flop circuit synchronously with an inverted signal of the input signal, and a logic circuit for receiving an inverted latch output signal outputted from the latch circuit and a register output signal of the [m+1]th flip-flop circuit and outputting the 1/[2m+1] frequency-divided signal.