Data processing apparatus having first bus with bus arbitration independent of CPU, second bus for CPU, and gate between first and second buses

An image processing apparatus containing a first bus, a second bus, a CPU connected to the first bus, a plurality of bus user units respectively connected to the second bus, a bus control unit connected with each of the plurality of bus user units and the CPU, and a bus connect/isolate gate unit connected with the first and second buses and the bus control unit. Each of the plurality of bus user units and the CPU contains a bus request signal sending unit for sending a bus request signal to the bus control unit when each of the plurality of bus user units and the CPU has a demand to use the second bus. The bus connect/isolate gate unit can isolate the first bus from the second bus, or connect the first bus with the second bus, under control of the bus control unit. The bus control unit receives the bus request signal from each of the plurality of bus user units and the CPU, determines one of the plurality of bus user units and the CPU, which sends the bus request signal to the bus control unit, as an acknowledged unit, sends an acknowledge signal to the acknowledged unit, makes the bus connect/isolate gate connect the first bus with the second bus when the CPU is the acknowledged unit, and makes the bus connect/isolate gate isolate the first bus from the second bus when the CPU is not the acknowledged unit.