Ferroelectric-based RAM sensing scheme including bit-line capacitance isolation

Ferroelectric-based RAM sensing scheme including bit-line capacitance isolation

A ferroelectric memory includes a bit line for developing a signal coupled to a ferroelectric memory cell. An integrated load capacitor and sense amplifier are also coupled to the bit line. An isolation circuit is included for selectively electrically isolating the bit line load capacitor from the s...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MEADOWS, BRETT, CHERN, WEN-FOO
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A ferroelectric memory includes a bit line for developing a signal coupled to a ferroelectric memory cell. An integrated load capacitor and sense amplifier are also coupled to the bit line. An isolation circuit is included for selectively electrically isolating the bit line load capacitor from the sense amplifier and ferroelectric memory cell during the active operation of the sense amplifier. The isolation circuit is compatible with both non-volatile ferroelectric and volatile dynamic memory operation.