Dram refresh controller with improved bus arbitration scheme

A cache controller with both burst and hidden refresh modes. In the burst mode, refresh requests are counted, but not acted on, until a predetermined number of refresh requests have been received. At that time, multiple refreshes are done in a single sequence. Although the amount of time taken for a...

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Bibliographische Detailangaben

Hauptverfasser:	CHEUNG, MILTON, CHAN, TZOYAO
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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