Dram refresh controller with improved bus arbitration scheme

A cache controller with both burst and hidden refresh modes. In the burst mode, refresh requests are counted, but not acted on, until a predetermined number of refresh requests have been received. At that time, multiple refreshes are done in a single sequence. Although the amount of time taken for actually refreshing the memory is the same, the time needed for arbitration to obtain control of the necessary busses is reduced, giving an overall savings of time. In the hidden refresh mode, a refresh is done, but no hold signal is sent back to stop the CPU while the refresh is being done. Circuitry is provided which allows local memory accesses, but holds other memory accesses until the refresh is completed. Thus, local memory accesses, which expect data quickly, are not inhibited and other memory accesses, which the CPU expects may take some time, can be held up without the CPU knowing.