Architecture of circuitry for generating test mode signals
An arrangement for generating signals for generating a particular set of test conditions within a digital circuit including a plurality of latches for storing individual bits of data representing individual operations to be accomplished within the digital circuitry, the latches each having input and...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | An arrangement for generating signals for generating a particular set of test conditions within a digital circuit including a plurality of latches for storing individual bits of data representing individual operations to be accomplished within the digital circuitry, the latches each having input and output terminals; the output terminals of each of the latches being connected to individual portions of the digital circuitry to effect an individual operation thereby; apparatus connected to the input terminals of the latches for setting individual selected ones of the latches to provide selected test conditions; and apparatus for transferring the condition of a selected number of the latches simultaneously to effect a selected test condition. |
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