Semiconductor wafer level package

A semiconductor wafer level package used to encapsulate a device fabricated on a semiconductor substrate wafer before dicing of the wafer into individual chips. A cap wafer is bonded to the semiconductor substrate wafer using a pre-patterned frit glass as a bonding agent such that the device is herm...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	HUGHES, HENRY G, SCOFIELD, JR., BROOKS L, STUCKEY, MARILYN J, BENNETT, PAUL T, ADAMS, VICTOR J
Format:	Patent
Sprache:	eng
Schlagworte:	ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR BASIC ELECTRIC ELEMENTS CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS,e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES,DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS CONVEYING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY HANDLING THIN OR FILAMENTARY MATERIAL PACKAGES PACKAGING ELEMENTS PACKING PERFORMING OPERATIONS SEMICONDUCTOR DEVICES STORING TRANSPORTING
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Beschreibung
Zusammenfassung:	A semiconductor wafer level package used to encapsulate a device fabricated on a semiconductor substrate wafer before dicing of the wafer into individual chips. A cap wafer is bonded to the semiconductor substrate wafer using a pre-patterned frit glass as a bonding agent such that the device is hermetically sealed inside a cavity. A hole in the cap wafer allows electrical connections to be made to the device through electrodes which pass through the frit glass seal.