System and method for preserving instruction granularity when translating program code from a computer having a first architecture to a computer having a second reduced architecture during the occurrence of interrupts due to asynchronous events

A computer program of complex instruction set code (CISC) is translated to produce a program of reduced instruction set code (RISC). Each CISC instruction is translated into a sequence of RISC instructions. The sequence includes in order four groups of instructions. The first group includes instructions that get inputs and place them in temporary storage. The second group includes instructions that operate on the inputs and place results in temporary storage. The third group includes instructions that update memory or register state and are subject to possible exceptions. The fourth group includes instructions that update memory or register state and are free of possible exceptions. When execution of the RISC program is interrupted by an asynchronous event, the RISC instruction being executed at the time of the interrupt is recorded and allowed to complete. The recorded instruction is checked against a bit map to determine whether it is a boundary instruction for the instruction sequence being executed, and if it is, then asynchronous event processing is permitted. If not, then a program counter for the RISC code is aligned with the next backup boundary instruction if any instruction remaining to be executed is subject to a possible exception. If no instruction subject to a possible exception is found, the remaining instructions in the sequence are executed while moving the program counter to the next forward boundary instruction and thereafter permitting asynchronous event processing.