N-dimensional multi-port memory

A three dimensional memory enabling both pixel and bit slice data to be stored and retrieved through different ports. A memory circuit (30) is divided into a lower memory block (32a) and an upper memory block (32b). Each memory block is organized into 256 rows *16 groups (pixel planes) of eight columns (bit planes). Eight bits of pixel data are stored at a selected row and pixel plane of the upper or lower memory block, and sixteen bits of pixel data are stored at a selected row and bit plane of the upper or lower memory block. Address bits determine the location of pixel data and bit slice data. A bit plane port is used to access data in the bit slice format and another port is used to access data in the pixel format. Bit slice data input through the bit plane port and stored in the memory circuit can be read as pixel data through the pixel port, and vice versa. By enabling image data stored in the memory circuit to be accessed as either pixel or bit slice data, retrieval of the image data in either representation is achieved without the need for an external serial-to-parallel or parallel-to-serial converter, greatly enhancing the speed by which the data stored in one representation is retrieved in the other.