Use of output impedance control to eliminate mastership change-over delays in a data communication network

An output resistance (RO) is situated at each output of a plurality of drivers communicating to a plurality of receivers via an interconnect network which is biased by a terminal supply voltage (VT). The output resistance RO eliminates the need for a wait period in a cycle, which wait period is usually required when mastership of the interconnect network changes over from one driver to another driver. The drivers and receivers are two-state devices. For a logic high, the drivers exhibit a virtually infinite resistance. Consequently, the interconnect network exhibits a high voltage VINT, which is approximately equal to the terminal supply voltage VT. Whereas for a logic low, the drivers sink current from the interconnect network, thereby pulling the interconnect network voltage VINT towards ground. Any signal below about (7/8)*VT is recognized by the receivers as a logic low, while any signal above this threshold is recognized as a logic high. In the case of a logic low, the voltage VINT is prevented from being pulled to ground by the output resistance (RO). The driver sinks enough current so that the voltage VINT is approximately equal to VT/2. Accordingly, if a change over occurs in a cycle after a logic low, the newly active driver can immediately drive a logic high or low onto the interconnect network, because the voltage VT/2 is readily available on the interconnect network. If the newly active driver wishes to drive a logic high, the driver exhibits infinite resistance, and the voltage VINT increases to VT. If the newly active driver wishes to drive a logic low, the driver sinks current, and the voltage VINT increases to only about (3/4)*(VT), which is recognized as a logic low. The voltage VINT will ultimately decrease to VT/2, thereby enhancing its disposition as a logic low.