Thin film transistor with an increased switching rate

A thin film transistor arranged in a matrix array with a strip type gate address line and a source signal line, comprising: an insulating layer formed on the gate address line; a semiconductor layer formed on the insulating layer, which serves as a channel conductive layer; the source signal line fo...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SOHN, JEONGHA, BAE, BYUNGSEONG
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A thin film transistor arranged in a matrix array with a strip type gate address line and a source signal line, comprising: an insulating layer formed on the gate address line; a semiconductor layer formed on the insulating layer, which serves as a channel conductive layer; the source signal line formed passing by one side of the channel layer; a first drain electrode arranged in parallel with, and spaced from, said source signal line; and at least one pixel electrode connected to any one side of the drain electrode.