Thin film transistor with an increased switching rate
A thin film transistor arranged in a matrix array with a strip type gate address line and a source signal line, comprising: an insulating layer formed on the gate address line; a semiconductor layer formed on the insulating layer, which serves as a channel conductive layer; the source signal line fo...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | A thin film transistor arranged in a matrix array with a strip type gate address line and a source signal line, comprising: an insulating layer formed on the gate address line; a semiconductor layer formed on the insulating layer, which serves as a channel conductive layer; the source signal line formed passing by one side of the channel layer; a first drain electrode arranged in parallel with, and spaced from, said source signal line; and at least one pixel electrode connected to any one side of the drain electrode. |
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