Logic array having high frequency internal clocking
A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a se...
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| creator | FRANCE MICHAEL G FITZPATRICK MARK E GRAHAM ANDREW C BURD ROBERT C |
| description | A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US5204555A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US5204555A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US5204555A3</originalsourceid><addsrcrecordid>eNrjZDD2yU_PTFZILCpKrFTISCzLzEtXyMhMz1BIK0otLE3NS65UyMwrSS3KS8xRSM7JT84GKuBhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfGhwaZGBiampqaOxoRVAABYnyvb</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Logic array having high frequency internal clocking</title><source>esp@cenet</source><creator>FRANCE; MICHAEL G ; FITZPATRICK; MARK E ; GRAHAM; ANDREW C ; BURD; ROBERT C</creator><creatorcontrib>FRANCE; MICHAEL G ; FITZPATRICK; MARK E ; GRAHAM; ANDREW C ; BURD; ROBERT C</creatorcontrib><description>A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; CONTROL OR REGULATING SYSTEMS IN GENERAL ; CONTROLLING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS ; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS ; PHYSICS ; PULSE TECHNIQUE ; REGULATING</subject><creationdate>1993</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19930420&DB=EPODOC&CC=US&NR=5204555A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19930420&DB=EPODOC&CC=US&NR=5204555A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FRANCE; MICHAEL G</creatorcontrib><creatorcontrib>FITZPATRICK; MARK E</creatorcontrib><creatorcontrib>GRAHAM; ANDREW C</creatorcontrib><creatorcontrib>BURD; ROBERT C</creatorcontrib><title>Logic array having high frequency internal clocking</title><description>A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>CONTROL OR REGULATING SYSTEMS IN GENERAL</subject><subject>CONTROLLING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</subject><subject>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>REGULATING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1993</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD2yU_PTFZILCpKrFTISCzLzEtXyMhMz1BIK0otLE3NS65UyMwrSS3KS8xRSM7JT84GKuBhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfGhwaZGBiampqaOxoRVAABYnyvb</recordid><startdate>19930420</startdate><enddate>19930420</enddate><creator>FRANCE; MICHAEL G</creator><creator>FITZPATRICK; MARK E</creator><creator>GRAHAM; ANDREW C</creator><creator>BURD; ROBERT C</creator><scope>EVB</scope></search><sort><creationdate>19930420</creationdate><title>Logic array having high frequency internal clocking</title><author>FRANCE; MICHAEL G ; FITZPATRICK; MARK E ; GRAHAM; ANDREW C ; BURD; ROBERT C</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US5204555A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1993</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>CONTROL OR REGULATING SYSTEMS IN GENERAL</topic><topic>CONTROLLING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</topic><topic>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>REGULATING</topic><toplevel>online_resources</toplevel><creatorcontrib>FRANCE; MICHAEL G</creatorcontrib><creatorcontrib>FITZPATRICK; MARK E</creatorcontrib><creatorcontrib>GRAHAM; ANDREW C</creatorcontrib><creatorcontrib>BURD; ROBERT C</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FRANCE; MICHAEL G</au><au>FITZPATRICK; MARK E</au><au>GRAHAM; ANDREW C</au><au>BURD; ROBERT C</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Logic array having high frequency internal clocking</title><date>1993-04-20</date><risdate>1993</risdate><abstract>A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY FUNCTIONAL ELEMENTS OF SUCH SYSTEMS MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS PULSE TECHNIQUE REGULATING |
| title | Logic array having high frequency internal clocking |
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