Logic array having high frequency internal clocking

A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a se...

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Bibliographische Detailangaben
Hauptverfasser:	FRANCE, MICHAEL G, FITZPATRICK, MARK E, GRAHAM, ANDREW C, BURD, ROBERT C
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY FUNCTIONAL ELEMENTS OF SUCH SYSTEMS MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS PULSE TECHNIQUE REGULATING
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Beschreibung
Zusammenfassung:	A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.