Memory based line-delay architecture

A digital line delay architecture is provided that requires a minimum of chip space, has low power requirements, is variable or programmable in length, and is flexible to permit changes in aspect ratio. The digital line delay architecture is self-multiplexing and therefore requires no external addressing for the multiplexing function, and is particularly suited for use as a video line delay in a single chip digital image processing device. In particular, a pointer unit is employed to sequentially address a plurality of word storage locations provided in a storage unit. The pointer unit includes a number of shift-registers that sqeuentially shift a logic "1" along the length of the pointer unit to accomplish the addressing.