Scan path circuit

A scan path circuit, to be integrally inserted in an arbitrary place of a logic circuit, for detecting faults of the logic circuit. The scan path circuit includes: a first switch connected to a data-in for receiving data from the logic circuit; a second switch connected to the first switch and to a data-out for sending data to the logic circuit; a third switch connected to the data-out; a first latch connected to a scan-in for inputting testing data and storing the data and connected to the third switch for outputting the data to the logic circuit; and a second latch for inputting and storing the data returned from the logic circuit. The circuit is so constructed that the connection of the latches and the logic circuit is controlled so as to detect faults of the circuit during scanning operation and to directly connect the data-in with the data-out during normal operation.