Multi-frequency clock generation with low state coincidence upon latching

A clocking circuit connected to a processor for regulating processor operation and including a control circuit that produces a clock signal at a first frequency or for producing a clock signal at a designated one of a plurality of other selectable frequencies in response to a change signal from the processor. The control circuit is connected to a designating circuit that provides a signal to the control circuit to designate one of the selectable frequencies. In the preferred embodiment, the clocking circuit includes a register addressable by the processor and a frequency generator that generates several signals having unique frequencies. The processor may designate one of the frequencies as the clocking frequency by providing the appropriate data to the register. Upon the occurrence of an external event such as a DMA request or an interrupt, the control circuit will provide the clocking signal at a predetermined frequency.