Memory drive device and method

In a memory drive device comprising a semiconductor memory, a memory control circuit for controlling the operation of the memory, the control circuit including a reset terminal and operative to initialize the internal status when a reset signal of a predetermined level is applied to the reset terminal, and a main power supply for delivering a power to the memory and to the memory control circuit, the memory drive device comprises a comparator circuit for comparing a power feed voltage from the main power supply with a predetermined threshold voltage and for detecting that the power feed reaches predetermined voltage to output a detection signal, and a reset circuit responsive to a detection signal from the comparator circuit to generate a reset signal of a predetermined logic level for at least a predetermined time period to apply a reset signal to the reset terminal. At the time when the main power supply is turned on, or at the time of recovery of service interruption, for at least a predetermined time period from the time when the output level of the main power supply has a predetermined threshold voltage irrespective of a rise speed of the main power supply voltage, a reset signal of a predetermined logic level is applied to the memory control circuit.