Bus receiver power-up synchronization and error detection circuit
A bus receiver power-up synchronization circuit synchronizes the receipt of parallel data messages transferred asynchronously as three byte words preceded and succeeded by idle bytes so as to receive complete and not partial messages. Also, the receiver scrutinizes the messages for faults and for to...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A bus receiver power-up synchronization circuit synchronizes the receipt of parallel data messages transferred asynchronously as three byte words preceded and succeeded by idle bytes so as to receive complete and not partial messages. Also, the receiver scrutinizes the messages for faults and for too many or too few bytes. |
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