Process for fabricating a control gate for a floating gate FET

A process of forming a floating gate field-effect transistor having a multi-layer control gate line is disclosed. The multi-layer control gate line includes a first polysilicon layer, a silicide layer provided on the first polysilicon layer, and a second polysilicon layer provided on the silicide la...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: WANG, HSINGYA A
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A process of forming a floating gate field-effect transistor having a multi-layer control gate line is disclosed. The multi-layer control gate line includes a first polysilicon layer, a silicide layer provided on the first polysilicon layer, and a second polysilicon layer provided on the silicide layer. The first and second polysilicon layers are formed as undoped polysilicon to improve the adhesion of the polysilicon layers to the silicide layers sandwiched therebetween. After all three layers are formed, the polysilicon layers are doped in an environment including POCl3. Because the first and second polysilicon layers are formed as undoped layers, all three layers of the control gate line may be formed using a single pump-down.