Semiconductor memory device

A main row decoder for driving main word lines in a main memory cell array includes partial decoders the number of which is equal to the number of the main word lines. Each partial decoder includes a NAND gate for receiving row address signals, an inverter for driving a corresponding main word line in response to an output from the NAND gate, a fuse element connected between the output terminal of the NAND gate and the input terminal of the inverter, and a MOS transistor connected between the input terminal of the inverter and a power supply voltage.