Resettable latch circuit
A reset circuit incorporated into a latch circuit which comprising a follow portion and a hold portion and generates an output signal at an output terminal in response to an input data signal and a clock signal. A reset signal is applied, via a diode, to the output terminal which causes the output t...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A reset circuit incorporated into a latch circuit which comprising a follow portion and a hold portion and generates an output signal at an output terminal in response to an input data signal and a clock signal. A reset signal is applied, via a diode, to the output terminal which causes the output terminal to immediately assume the state of the reset signal without any intervening gate delay. |
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