Gate processor arrangement for simulation processor system

A gate processor arrangement for a logic simulation processor system includes a new event buffer memory (500c) for storing an event at a timing ta for a predetermined logic element in a section of a logic network; a fanout device (500d) for holding connection information for the predetermined logic element in the section of the logic network and reading the data of the predetermined logic element precedingly at a timing t, the input data of the predetermined logic element being changed at a timing "t+1"; and an evaluation gate buffer memory (500g) having a plurality of evaluation gate memory portions (500g1, 500g2) able to be connected with the fanout device and an evaluation device (500e). The arrangement also includes a net status memory (500f) for holding net status information corresponding to input data and output data of a predetermined logic element in the section of the logic network; and the said evaluation device (500e) responsive to the output of the evaluation gate buffer memory (500g) for reading the data in the net status memory (500f), generating information for the change of the network status at a timing "t+1", and supplying the generated information to an event transmission network (2) and/or the new event buffer memory (500c).