Process for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chip

A process is used to form in a common substrate (12) a PMOS transistor (200) of the lightly-doped drain (LDD) type, an NMOS transistor (100) of the LDD type and a vertical n-p-n bipolar transistor (300). In particular: the steps used to form an n-type well (214) for the PMOS transistor (200), and an...

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Bibliographische Detailangaben

Hauptverfasser:	ROWLANDS, III, PAUL R, SCHNABEL, DOUGLAS R, MANN, JONATHAN D, PARRISH, JACK D, KOSIAK, WALTER K
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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