Process for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chip

A process is used to form in a common substrate (12) a PMOS transistor (200) of the lightly-doped drain (LDD) type, an NMOS transistor (100) of the LDD type and a vertical n-p-n bipolar transistor (300). In particular: the steps used to form an n-type well (214) for the PMOS transistor (200), and an n-type drain extension well (114) for the NMOS transistor (100), are also used to form the n-type collector (314) of the bipolar transistor (300); the steps used to form the p-type extension well (208) for the PMOS transistor (200) are also used to form the p-type base (308) of the bipolar transistor (300), the source/drain implantation step for the NMOS transistor (100) is also used to form the emitter (310) and a contact region (312) for the collector of the bipolar transistor (300); and the source/drain implantation step for the PMOS transistor (200) is used to form a contact region (311) for the base of the bipolar transistor (300).