Multiprocessor storage serialization apparatus

Storage serialization apparatus in a multiprocessor computer system enables multiple processors to concurrently execute instructions which access storage without materially affecting performance by keeping the amount of storage locked to a minimum, i.e., a page. The duration of serialization need be only for one instruction execution time and only instruction operands need be accommodated for serialization. Each storage request is intercepted by an associative register stack where there are two registers for each operand, one of the two being for operand page crossings. After a processor has locked access to an area of storage, execution of the instruction begins and all other processor are locked out but only with respect to that locked area. Other processors can access other storage areas during the instruction cycle. When the execution of the instruction completes, the processor releases the locked area of storage by invalidating the entries in its associative register array. A mechanism arbitrates and breaks possible deadlocks.