Charge-coupled device with varible storage capacity and constant clock frequency

Charge-coupled device with varible storage capacity and constant clock frequency

In a one-electrode/bit SPS CCD memory, a capacity reduction can be obtained by phase shift of one or more clock voltages. For an n-phase system with N groups of n electrodes, the storage capacity can thus be reduced stepwise from at most N(n-1) bits to N(n-2) bits, etc. The stay time of the bits sto...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: PFENNINGS, LEONARDUS C. M. G, STEENHOF, FRITS A
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PICTORIAL COMMUNICATION, e.g. TELEVISION
SEMICONDUCTOR DEVICES
STATIC STORES
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Beschreibung
Zusammenfassung:In a one-electrode/bit SPS CCD memory, a capacity reduction can be obtained by phase shift of one or more clock voltages. For an n-phase system with N groups of n electrodes, the storage capacity can thus be reduced stepwise from at most N(n-1) bits to N(n-2) bits, etc. The stay time of the bits stored is reduced by a corresponding factor, as a result of which the clock frequency in the series registers need not be changed. By this reduction, the memory is more particularly suitable for storing television pictures both in the 625 lines system and in the 525 lines system.