Nonvolatile memory device with a high number of cycle programming endurance

An electrically alterable, non volatile memory device capable of enduring a high number of cycles utilizes an array of "semidouble" cells, each formed by a pair of elementary EEPROM cells connected substantially in parallel and a single select transistor. A special program lines biasing circuit generating a bias voltage (VCG) representative of a condition wherein one of the two elementary EEPROM structure is broken and sense amplifiers comprising a comparator circuit (0, 1, 2...7) comparing the current flowing through an addressed semidouble memory cell with the current flowing through a reference cell comprising a pair of virgin EEPROM type elementary cells ensure operability of each bit of the memory also when one of the two elementary cells supporting the bit fails. Differently from known memories, only the EEPROM structure is duplicated while column lines (BL00...BL07), select lines and ancillary circuitry don't require duplication.