Circuit arrangement with a processor and at least two read-write memories

In order for any failure of the power supply unit for two read-write memories which are operable in parallel, not to result in irreversible damage to data, two parallel power supply circuits are provided for the operation of the memories. Each power supply circuit is capable of supplying the operating current of one of the memories and the standby current of the remaining memory. Each of the power supply circuits in the power supply is buffered with capacitors in such a manner that, upon a fault in one of the power supply circuits, the output voltage, as soon as the capacitive buffer declines from a normal operating voltage to a threshold voltage and to a minimum operating voltage, data secure current reducing steps are taken. The capacitive circuits and threshold voltages are selected such that the period of time the voltage takes to decline from the threshold to the minimum operating voltage is longer than the time required to complete the present read-write operation and to save the relevant data into the memory. One of the memories is then put into standby mode by a monitoring device as the output voltage declines to the threshold voltage leaving only one active memory which can be operated from one of the two memory power supply circuits.