Hardware interpreter for finite state automata

Apparatus and method for monitoring transactions on a high speed interface bus and for selectively storing information about such transactions together with the time of such transaction and the state of the automation. The apparatus comprises two parallel memories for respectively storing a regular table and a default table, and a memory selector for choosing between the table data of the two memories. A bus trap stores data information obtained from the bus and compares the stored information with a stored data template. A transition detector receives control signals from the bus and generates clock signals used by other system elements upon the detection of a transition. A hash coder utilizes a hash key together with state information to generate an address for entering the regular table memory. A state latch stores an address provided by the memory selector for the default table. A sample collector and sample queue component stores the state information together with the data and control information obtained from the monitored bus and a time stamp provided by a time stamp generator. A DMA output control provides the sample information to a display computer. The method monitors the interface bus interactions and selectively stores the monitored data and control signals when an analysis of those signals indicate that a transition has occurred. Two parallel, distinct look-up tables store state information and default information and are substantially entered at the same time to provide separate sets of table data. One set of table data is chosen depending upon predetermined criteria.